(1) Field of the Invention
The present invention relates to a process for making an array of metal-insulator-metal (MIM) crown storage capacitors for dynamic random access memory (DRAM) devices, and more specifically for making an array of improved MIM capacitor bottom electrodes that are recessed to reduce memory cell area and increase circuit density. The method utilizes a sequence of process steps that includes a novel planarization process for making the bottom electrodes with a more uniform recess depth in insulator openings for better process control across the wafer. This provides a more uniform capacitance for the array of capacitors across each chip and across the wafer (substrate).
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronics industry for storing data. The DRAM circuit includes an array of memory cells, each cell consisting of a single capacitor and a single transfer transistor. Typically the transfer transistor is a field effect transistor (FET). Binary data (1 and 0) are stored as charge on the capacitors, and the transfer transistors are used to retain the charge. During the read cycle the transfer transistors are used to interrogate the cell by means of an array of bit lines. Two types of memory cells that are commonly used include a cell having a trench capacitor formed in the substrate under the FETs, and a cell having a stacked capacitor that is built on and over the FETs on the substrate. In the coming years the number of cells on a DRAM chip is expected to exceed 1 Gigabit. This increase is a result of the downsizing of feature size of the discrete devices using improved high-resolution photolithography, improved directional plasma etching, and more recently self-aligning techniques. One method of achieving this higher density is to form crown capacitors in which the bottom electrodes are formed in an array of openings in an insulating layer over the array of capacitor node contacts to the underlying array of memory cell areas.
One type of stacked capacitor that is commonly used is the crown-shaped capacitor shown in FIG. 1. This type of capacitor is formed by depositing an interlevel insulating layer 12 on a substrate 10 having semiconductor devices, such as FETs. An array of node contacts 14, formed, for example of polysilicon, are formed in openings in the insulating layer 12 to the cell areas on the substrate 10. The FETs are not shown, and only one of the node contacts is depicted to simplify the drawing. A second insulating layer 16 is deposited, and recesses or wells are etched in layer 16 aligned over and down to the node contacts. A conformal conducting layer 18 is deposited and a sacrificial layer, such as a polymer (not shown), is used to fill the recesses. The layers are then etched or polished back to form the capacitor bottom electrodes 18, and the polymer is selectively removed. A thin capacitor dielectric film 20 is deposited. A second conducting layer 22 is deposited and a photoresist mask and etching are used to pattern the capacitor top electrodes. One disadvantage of making a capacitor by this method is that a masking step is required to pattern the top electrode, which results in increased DRAM cell size. Also, the process is not compatible with a damascene process.
An alternative prior-art approach to making an array of crown capacitors is shown in FIG. 2. In this approach the process is similar to the process shown in FIG. 1, except that the bottom electrodes 18 are recessed below the top edges of the recesses or wells in the second insulating layer 16. A thin capacitor dielectric layer 20 is deposited over the recessed bottom electrodes 18. A second conducting layer 22 is deposited and polished back to the top surface of the second insulating layer 16 to form self-aligned top electrodes 22 in the recesses, as shown in FIG. 2. This form capacitors having smaller surface areas and that results in higher density of memory cells and is also compatible with a damascene process.
The prior-art approach of making an array of crown-shaped capacitors having recessed bottom electrodes, as shown in FIG. 2, is achieved by the following method. After depositing a conformal first conducting layer 18 for the bottom electrodes, a sacrificial layer 26, such as a polymer or photoresist, is spin coated. Because of the topography on the substrate 10, the sacrificial layer 26 is non-uniform. For example, layer 26 is generally thicker near the edge of the array of cells on the DRAM chip, as depicted by area A in FIG. 3, and layer 26 is generally thinner over the closely spaced array of cells for the capacitors at the center of the DRAM chip, as depicted by the thinner area B. When sacrificial layer 26 is etched or polished back to expose the first conducting layer 18 to recess the bottom electrodes 18, the sacrificial layer has varying depths as depicted by the dashed lines D1, D2 at the center of the DRAM chip compared to the depth depicted by D3 and D4 in the recesses for the capacitors at the edge of the array on the chip. When the first conducting layer 18 is etched to recess the bottom electrodes, as shown in FIG. 2, the variation of the depths D1, D2, D3, and D4 of the sacrificial layer results in varying heights of capacitor bottom electrodes across the array of memory cells and also across the wafer. When the DRAM devices are completed, the large variations in the area of the bottom electrodes results in large variations in capacitance, which is undesirable.
Numerous methods of making high density DRAM devices having crown capacitors have been reported in the literature. For example, Jeng et al. in U.S. Pat. No. 6,168,987 B1 describe a method for fabricating a crown capacitor that is self-aligned to both the underlying bit lines and word lines. Jeng's array of bottom electrodes is made in an insulating layer that is later removed. Liaw, U.S. Pat. No. 6,344,392 B1, teaches a method of making a stacked capacitor having a monolithic fin structure. The structure is achieved by depositing a multilayer of different insulators with openings for capacitors, and the insulators in the openings are etched at different rates to form a mold for a fin-shaped capacitor. The bottom electrodes for the capacitors are formed in the openings. Then the multilayer of different insulators is removed to form free-standing bottom electrodes. Forming self-aligned top electrodes is not addressed. Linliu, U.S. Pat. No. 6,180,483 B1, describes a method for making multiple-crown capacitors that cannot accommodate recessing the bottom electrodes and forming self-aligned top electrodes. U.S. Pat. No. 6,177,351 B1 to Beratan et al. teaches a method of etching a thin perovskite layer overlying a second material without substantially etching the second material. However, none of the cited references addresses the prior-art problem described above.
Therefore, there is still a strong need in the industry to make crown-shaped capacitors for DRAM devices that have capacitance that lie within acceptable manufacturing tolerances.